Autonomous Testing of Reconfigurable Evolved Circuits Using Embedded Ip Core Units

In this paper, a novel domain specific reconfigurable architecture and an associated design methodology which provides flexibility as well as autonomous restructuring of Processing Elements (PEs) of Virtual Reconfigurable Circuits (VRCs) is proposed. The proposed VRC and evolutionary algorithm is described in VHDL independently of a target platform i.e. as a soft IP core, and realized in the FPGA based hardware. This approach is based on functional level evolution whose architecture is evolved optimally with non–linear functions using Genetic Algorithm (GA). The studies done in this work will assist in estimating the VRCs influence in the integration of Field Programmable Gate Array (FPGA) based evolvable systems and provide high performance benefits. Keywords-Autonomous Restructuring, FPGA Virtual Reconfigurable Circuits